Deo Brat Singh
Summary
Proactive Director produces high-quality and robust semiconductor HV (Bulk/SOI) and RF (Si-Ge based BiCMOS) technologies by applying determination and attention to detail. Performance-oriented and enterprising leader with organized nature and analytical problem-solving approach.
Vast experience in semiconductor industry for Process transfer/Development/Integration experience of various processes (HV SOI and bulk BCD technology, Analog, logic, Trench MOS and Si-Ge based BiCMOS technology for RF applications
Overview
22
22
years of professional experience
Work History
Director, Technology Development
Silicon Manufacturing Company Pte Ltd, SSMC
10.2019 - Current
- 31 People reporting
- Responsible for managing technology development and technology roadmap for High voltage and Si-Ge based BiCMOS RF technologies
- Responsible for managing tape out engineering and operation
- Responsible for managing device characterization and wafer test operation
Deputy Director, Technology Development
Silicon Manufacturing Company Pte Ltd, SSMC
02.2017 - 10.2019
- 0.14um HV bulk technology development
- 0.14um SOI based HV technology development
- 0.25um Si-Ge based BiCMOS technology transfer for RF applications
- 0.14um Si-Ge based BiCMOS RF technologies development for high performance RF applications
Manager, Process Integration
Global Foundries 200mm BEU
04.2013 - 02.2017
- 0.18um 10-30V ULL and Isolated BCD Lite Process (Low Rdson) Internal transfer and Ramp
- 0.18um 16-30V Isolated BCD Lite Process Internal Transfer and Ramp
- 0.18/0.16um 40V BCD Process Development/ External Transfer
- 0.18um ULL analog and DDD process maintenance, improvement, new device integration
- 0.18um Si Photonics Process Co-development
Sr. Section Manager, Process Integration
Global Foundries 200 BEU
04.2011 - 03.2013
- 0.35um Embedded EEPROM (Standard bit cell) process maintenance and improvement
- 0.35um Embedded EEPROM (Shrink bit cell) process integration optimization and ramp
- 0.30um 30V BCD Process Development/ External Transfer
- 0.7um Trench process development/External transfer and ramp
Section Manager, Process Integration
Global Foundries 200mm BEU
01.2010 - 03.2011
- 0.35um Embedded EEPROM (Standard bit cell) process maintenance and improvement
- 0.35um Embedded EEPROM (Shrink bit cell) process integration optimization and ramp
- 0.5um EEPROM and Mask ROM process maintenance and improvement
Principle Engineer, Process Integration
Global Foundries 200mm BEU
10.2007 - 12.2009
- Integrated the 32V LDNMOS process in 0.35um analog process technology
- Integrated the 20V LDPMOS and 6V Zener Diode in the 0.35um 20V LDNMOS process
Sr Engineer, Process Integration
Global Foundries, 200 mm BEU
02.2005 - 09.2007
- High voltage LDNMOS (20V) process integration and production ramp
- High voltage DDD CMOS (18V) process maintenance and improvement
R & D Engineer
Semiconductor Complex Limited
Chandigarh, India
02.2000 - 01.2005
- 0.8um HV CMOS process development
- Development of 1.2um 30V CMOS process
- Integration of high beta substrate collector NPN and collector isolated PNP in the 3.0 um (15V) CMOS process using the existing layer in the process
Education
M. Tech - Solid State Technology
Indian Institute of Technology (I.I.T)
India12.1999
Master of Science - Solid State Physics
Banaras Hindu University (BHU)
India07.1996
Skills
- Attention to Detail
- Task Delegation
- Time Management
- Problem Solving
- Schedule Management
- Administrative Functions
Accomplishments
- 4 trade secretes and 3 publications in Semiconductor areas
Affiliations
Vast experience in semiconductor industry for Process transfer/Development/Integration experience of various processes (HV SOI and bulk BCD technology, Analog, logic, Trench MOS and Si-Ge based BiCMOS technology for RF applications. Hands on experience of device characterization, developing the quality and robust technologies and ramping of the processes with BIC yield.
People Manager since 2010. Capable of updating the knowledge. Capable of working with multi-cultural/multi-national team members.
Timeline
Director, Technology Development
Silicon Manufacturing Company Pte Ltd, SSMC
10.2019 - Current
Deputy Director, Technology Development
Silicon Manufacturing Company Pte Ltd, SSMC
02.2017 - 10.2019
Manager, Process Integration
Global Foundries 200mm BEU
04.2013 - 02.2017
Sr. Section Manager, Process Integration
Global Foundries 200 BEU
04.2011 - 03.2013
Section Manager, Process Integration
Global Foundries 200mm BEU
01.2010 - 03.2011
Principle Engineer, Process Integration
Global Foundries 200mm BEU
10.2007 - 12.2009
Sr Engineer, Process Integration
Global Foundries, 200 mm BEU
02.2005 - 09.2007
R & D Engineer
Semiconductor Complex Limited
02.2000 - 01.2005
M. Tech - Solid State Technology
Indian Institute of Technology (I.I.T)
Master of Science - Solid State Physics
Banaras Hindu University (BHU)
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